SDR Forum Workshop on Rapid FPGA Development for Wireless Applications –
IP Cores, Tools, and Standards Agenda - September 17, 2009
  

This workshop will arm communications systems engineers, application developers and other technologists with the knowledge they need to implement software defi ned and cognitive radio systems utilizing FPGA based processing, and allow them to work with leading experts in FPGA design processes and tools to reduce the time and cost associated with FPGA development. The workshop will begin with an introductory keynote from Xilinx, followed by presentations by leading IP and application developers for FPGAs. The morning session will conclude with a panel discussion on exploring design requirements for FPGAs. The afternoon session will begin with presentations from leading tool and technology vendors supporting the development of FPGA based applications, to be followed by presentations from organizations promoting specifi cations also supporting FPGA based application development. The workshop will then conclude with a panel session exploring next steps in the evolution of FPGA development.

See Details for the Presentations below the table.

Thursday September 17
7:30-9:00	Breakfast and Registration
9:00-9:10	Welcome and Introduction – John Chapin, Chair of The SDR Forum
9:10-9:50	Keynote Address, “The Fastest, Most Cost Effective Way from Development to Production: FPGA or ASSP?” presented by Manuel Uhm, Director of Wireless Communications, Xilinx
9:50-10:15	“SDR Waveform development techniques for FPGA” presented by Chandrasekar Raj of ViaSAT
10:15-10:30	Coffee Break
10:30-10:55	“Automatic Synthesis of Flexible Multiprocessor Systems from Parallel Programs”, presented by Harold Ishebabi of Spectrum Signal Processing by Vecima
10:55-11:20	“An Open Source FPGA Infrastructure for Heterogeneous Component-Based Systems,” by Jim Kulp of Mercury Federal Systemsand Shep Siegel, of Atomic Rules, LLC
11:20-11:45	“Modular FPGA Design Approach to Achieve Source Level Portability” by Karl Wagner of Mitre
11:45-12:15	"Processors for Digital Signal Processing: A Changing Landscape" by Jeff Bier, President, BDTI
12:15-1:30	Networking Lunch and Demos
1:30-1:55	“Using MATLAB and Simulink for the Design and Early Verifi cation of Wireless Systems”, presented by John Irza of The Mathworks
1:55-2:20	“Architecturally Optimized IP and High Level Synthesis for Rapid Algorithm Implementation and Verification in FPGA and ASIC technologies” presented by Doug Johnson of Synopsis
2:20-2:45	“Next-Generation FPGA Middleware - Minimizing Latency in Multi-Processing SCA-Compliant Platforms” presented by Steve Jennis of PrismTech
2:45-3:00	Coffee Break
3:00-3:30	“MHAL for FPGA” presented by Don Stephens of the JTRS JPEO
3:30-4:00	“OCP Corporate Introduction” presented by Ian Mackintosh, President and Chairman of Open Core Protocol International Partnership (OCP-IP)
4:00-5:00	Panel Session/Roundtable Discussion – Closing the gap between FPGA developers and tools

Presentation Details

9:10 to 9:50 - Keynote Address - “The Fastest, Most Cost Effective Way from Development to Production: FPGA or ASSP?” presented by Manuel Uhm, Director of Wireless Communications, Xilinx

Abstract: FPGAs have continued to enable the maturity of SDR technology from defense to commercial wireless infrastructure. In particular, the increased development cost of semiconductors has favored FPGAs over ASICs and ASSPs in production to address medium-sized markets such as wireless infrastructure. In addition, standards such as CPRI, OBSAI and SRIO for connectivity, and 3GPP and WiMAX for air interface protocols, enable interoperability and foster the development of IP and a supporting ecosystem to enable rapid development and faster time-to-market. This presentation will provide an overview of how FPGAs are enabling SDR to be fi rst-to-market but also at lower BOM costs, including a competitive analysis vs. ASSPs.

About the Speaker: Manuel Uhm is the Director of Wireless Communications for Xilinx. Uhm is responsible for managing the commercial wireless business, as well as the product portfolio and roadmaps. He is also responsible for strategic marketing within the group and is an expert in market segmentation and sizing of FPGAs doing Digital Signal Processing. Uhm is also a member of the Board of Directors and Chair of the Markets Committee of the SDR (Software Defi ned Radio) Forum, as well as being on the Advisory Board for PennWell’s Military & Aerospace Electronics Forum.

Uhm joined Xilinx in 2004 and is a thought leader in identifying trends in software defi ned radio, digital signal processing, and other communications technologies. He has been published and quoted in numerous trade journals, such as Wireless Design & Development, Electronic Business, Wireless Systems Design, Portable Design, COTS Journal, Military Embedded Systems, and Military & Aerospace Electronics, as well as having spoken at a number of conferences and industry events, such as the LTE World Summit, Wireless China, SDR Forum Technical Conferences and Workshops, IDGA Software Radio Summit, IQPC SDR Europe, the Military Technologies Conference and the Military Radios Conference.

Prior to joining Xilinx, Uhm worked at Spectrum Signal Processing, Inc., a leader in Software Defined Radio subsystems, where he was responsible for the Marketing Department.

Uhm received his Master of Business Administration from Simon Fraser University and studied electrical engineering at Queen’s University.

9:50 to 10:15 “SDR Waveform development techniques for FPGA,” presented by Chandrasekar Raj of ViaSAT

Abstract: Software defined radio (SDR) technology utilizes reconfi gurable hardware platforms to support multiple waveforms and standards. The latest FPGA architectures provide massive amounts of digital logic, RAM, and DSP resources along with fl exible, highspeed, data interfaces. These resources make FPGAs an attractive solution for SDRs running at high bit rates, 300Mbps or more. Some waveforms have high enough bit rates or complexity to require the resources of multiple FPGAs. When this occurs, a WLP (Waveform Logic Partitioning) technique is important to achieve the desired interconnect speeds and for optimal resource utilization across FPGAs. One WLP technique is to break the waveform down into modular components (FFT, Filter, CORDIC, etc.) and design RTL modules for each component. Common programming and data interfaces are defi ned for all components making it easier to build components back into a full waveform. Care must be taken to design FPIM (FPGA Platform Independent Modules) to allow for ease in porting and reusability. ViaSat design teams design waveforms in such a modular fashion helping us to quickly build multiple waveforms for a given hardware platform. Effective WLP design for FPGAs and general principles for effi cient waveform design will be discussed along with techniques for power savings in FPGA based designs.

About the Speaker: Chandrasekar Raj is the Program Manager of ASIC & IP Strategic Business Unit for ViaSat. Raj is responsible for managing and marketing commercial ASIC business and IP products that include Digital Video Broadcast and Forward Error Correction IPs. He has over 13 years of experience in semiconductor design, strategic marketing and business management. Raj joined ViaSat/ECC in 2002 and was instrumental in setting up ASIC infrastructure. He managed design verifi cation for successful IpSTAR and SkyPHY ASICs. Prior to joining ViaSat, Raj consulted for NEC, Toshiba and was involved in Rx5900, Tx7901, Vr5432 and Vrc5477 MIPS processor design & verifi cation. Raj received his MBA in marketing from Case Western Reserve University and M.Eng in wireless communication & signal processing from University of Illinois. He is a senior member of IEEE and is the current chairman of IEEE Cleveland section.

10:30 to 10:55 “Automatic Synthesis of Flexible Multiprocessor Systems from Parallel Programs,” presented by Harold Ishebabi of Spectrum Signal Processing by Vecima

Abstract: Multiprocessor architectures on FPGAs can be customized so that the execution of specifi c computational intensive software implementations, such as signal processing, can be optimized for speed or area. The design of such customized architectures is very complex, consisting of steps such as architecture determination, task mapping, scheduling as well as low level FPGA synthesis, placement and routing. The large size of the design space and non-orthogonal design parameters necessitate design automation through highlevel synthesis to facilitate rapid explorations and implementations. This presentation introduces a design fl ow and high-level synthesis methodology that addresses these design challenges. The presentation will also cover software confi guration and automation of vendorspecific FPGA tools in the flow.

About the Speaker: Harold Ishebabi is an Application Engineer at Spectrum Signal Processing by Vecima. He provides technical support and application development for wireless systems, specializing in algorithm, fi rmware and FPGA development. His experience includes research on programmable ASICs, fi ne and coarse-grained FPGAs for software defi ned radios. Mr. Ishebabi received his combined Bachelors and Masters degree in Electrical Engineering from the University of Kaiserslautern, Germany. He is expecting to receive his PhD in Computer Engineering in October 2009 from the University of Potsdam, Germany, where he has been working as an external part-time student.

10:55 to 11:20 “An Open Source FPGA Infrastructure for Heterogeneous Component-Based Systems,” by Jim Kulp of Mercury Federal Systems and Shep Siegel, of Atomic Rules, LLC

Abstract: SDR, and the SCA specifi cation have proven the effi cacy of component-based development (CBD) for embedded systems. The optimal mix of processing technologies required in such systems is changing constantly, with technologies like multi-core, graphics processors, DSPs, and GPPs, all used in some cases. Except for the smallest and highest volume applications, FPGAs are almost always in this mix. This presentation will describe a close-to-the-metal open source CBD framework that supports SDR and SCA (as well as other embedded applications), across the range of technologies, focusing on the ever-present FPGA’s role in the technology mix. This framework is currently being applied across a range of applications from SDR/SATCOM to RCIED/SIGINT and Airborne exploitation and surveillance.

About the Speakers: Jim Kulp, Consulting Software Architect at Mercury Federal Systems, Inc., has for more than 20 years, designed/developed/architected embedded/realtime and component-based systems software, IP and related standards for various embedded markets including broadcast video processing, medical imaging, and defense. Since his role as software architect for Mercury Computer Systems’ multi-processor operating systems and middleware for more than 10 years, he has focused on advanced technologies and architectures in various DARPA, SDR, and other DoD efforts that combined CBD, heterogeneous, and parallel computing.

Shep Siegel, CTO of Atomic Rules, LLC, has enjoyed more than 25 years of practice in system architecture, applied digital signal processing and component sub-system design. During his tenure at Datacube, he began applying software techniques to hardware design. His contribution to transform coding, the invention of the Adaptive Zonal Coder, is cited by nearly 100 image and video processing patents. While at Mercury Computer Systems, Shep contributed to the development of IP comprising FPGA-based multicomputer nodes, led the adoption of the Open Core Protocol and Bluespec SystemVerilog, and helped transform these technologies into customer value.

11:20-11:45 “Modular FPGA Design Approach to Achieve Source Level Portability” by Karl Wagner of Mitre

Abstract: As the bandwidth of waveforms increase, more of the processing must be implemented in FPGAs. Porting complex waveforms implemented across multiple FPGAs to a new hardware platform is a complicated process. Partitioning, verifying, interfacing, and deploying the waveform can be challenging, even with support from the original waveform developers. While the components may involve complicated manipulation of the data stream, the transport between them is typically much simpler. It can be abstractly defined in terms of data flow characteristics qualified by various properties of the targeted hardware platform. If the interface between the components of the system is well defined, automated tools can easily create the required transport based on a high level structural view of the system. This paper advocates a structured approach to waveform design which balances the need of the Government for transparency to optimize the waveform porting and the need of the contractor to protect their intellectual property (IP).

About the Speaker: Karl Wagner is a Lead Digital Hardware Engineer for the MITRE Corporation. He has been architecting, designing and implementing FPGA based communications systems for over 15 years. As a member of MITRE's Programmable Radio Technology Laboratory team, his recent efforts include the development and prototyping of a design methodology to enhance portability and reuse of FPGA based IP in signal processing systems.

11:45 to 12:12 "Processors for Digital Signal Processing: A Changing Landscape" by Jeff Bier, President, BDTI

Abstract: For most of the past 25 years, designers of demanding, digital-signal-processing-centric systems have largely relied on ASICs and digital signal processors (DSPs) as their main processing engines.  Lately, however, the landscape of processing engine options has been shifting radically.  As single-core DSPs have reached the point of diminishing returns, established processor vendors and start-ups alike have been increasingly relying on multi-core architectures.  But multi-core architectures bring significant challenges in the realm of software development methodologies and tools.  Meanwhile, massively parallel architectures, in the form of FPGAs and GPUs, are increasingly seeing use as DSP engines, but these technologies bring their own development challenges.  And, as digital signal processing applications become more complex (and incorporate increasing amounts of non-signal-processing functionality) general-purpose CPUs are becoming an attractive option for some applications.  In this presentation, Jeff Bier will present highlights of some of BDTI's recent and ongoing evaluations of tradeoffs and trends in processing engines for signal processing applications.

1:30 to 1:55 “Using MATLAB and Simulink for the Design and Early Verification of Wireless Systems,” presented by John Irza of The Mathworks

Abstract: Modern wireless system design has become increasingly more challenging, owing to the wide range of standards that a single system is often required to support. Even for a single standard system, the complexity of current-day standards require the ability to implement a variety of modulation schemes, coding and equalization methods, and control and adaption techniques. In this presentation we will demonstrate the modeling and simulation of a wireless system which includes system level effects such RF nonlinearities. The need-for and advantages-of early verifi cation of a design will be highlighted through the use of system simulations that include RF impairments, the effects of fi xed-point implementation, and the utilization of legacy HDL code in a co-simulation environment. A methodology will be presented which uses DSP and/or FPGA hardware-in-the-loop as part of the early verifi cation approach to design.

About the Speaker: John Irza is a Technical Marketing Manager for The Mathworks communications products. His areas of focus include Cognitive Radio and Software Defi ned Radio, WiMAX and LTE systems, radar and sonar signal processing, and electronic warfare systems. Prior to joining The MathWorks in 2007, he was with Bluefi n Robotics where he was a systems engineer integrating acoustic and RF communications systems into unmanned undersea vehicles. He began his professional career in 1984 at Draper Laboratory as a member of the technical staff, specializing in sonar and GPS systems for manned and unmanned undersea vehicles.

1:55 to 2:20 “Architecturally Optimized IP and High Level Synthesis for Rapid Algorithm Implementation and Verification in FPGA and ASIC technologies” presented by Doug Johnson of Synopsis

Abstract: This presentation outlines a model-based high level synthesis (HLS) methodology that enables a single algorithm model to drive architecturally optimized implementation and verifi cation across multiple FPGA and ASIC technologies. The heart of the flow is a user-extensible library of IP that abstracts architecture and technology-dependent implementation details allowing easy high level design and simulation, but is also synthesizable with a high level synthesis engine that can take advantage of architectural and target optimizations at the system and IP level. The result is a consistent entry point for waveform algorithm design that is portable with automatic optimization and verification for multiple targets.

About the Speaker: Doug Johnson is a Staff Applications Consultant and DSP Product Specialist with the Synplicity Business Group of Synopsys, Inc. He is responsible for application engineering and product support for Synopsys’ high-level synthesis, FPGA and ASIC logic synthesis and system-level design capture software products. Mr. Johnson has more than 30 years of experience in communication design engineering, electronic design automation (EDA) tools, applications engineering, digital signal processing (DSP) design, intellectual property (IP) licensing and sales account management. He has a BSEE from the University of Illinois at Urbana-Champaign.

2:20 to 2:45 “Next-Generation FPGA Middleware - Minimizing Latency in Multi-Processing SCA-Compliant Platforms,” presented by Steve Jennis of PrismTech

Abstract: The SCA specification allows for two approaches to SCA waveform component compliance on FPGA: an abstraction layer (sometimes referred to as Modem Hardware Abstraction Layer or MHAL) or CORBA (as on GPP and DSP). In first-generation SCA radios a custom MHAL was often used, but introduced signifi cant latency into the radio, as well as a non-standard interface layer with all the associated support and maintenance issues. CORBA was not then an option as a hardware implementation of an ORB was not available. However, a hardware ORB implementation (Integrated Circuit ORB or ICO) has now been developed by PrismTech and tested by Selex Communication. The results of this testing show signifi cantly lower latency as well as a relatively small ‘gate or logic element’ footprint for ICO. This is not surprising given the much more effi cient architecture of ICO versus MHALs. Of course ICO is also based on an accepted middleware Standard, as opposed to the proprietary nature of MHALs. This presentation will include the results of this testing, explain how such low latencies and footprints are achievable, and invite participation in the next phase of ICO development and standardization. The ICO Joint Industry Project (ICO JIP) is already supported by Selex Communications, Altera, and PrismTech and is open to any other participants and observers interested in influence over, and early access to, ICO technology for next-generation SCA radio designs.

About the Speaker: Steve Jennis joined PrismTech when it was a ‘start-up’ after a 16 year career with Texas Instruments. Steve has been a key executive in growing PrismTech’s annual revenues to over $15M per annum and he led its entry into SDR COTS software in 2006. Today PrismTech has personnel in seven countries and is a recognized technology leader in software platforms and tools for real-time, distributed, and embedded systems. Steve holds an Honors degree in Physics and a post-graduate Diploma in Industrial Management from Loughborough University in England. Steve and his family have lived in Texas for the past 12 years.

3:00 to 3:30 “MHAL for FPGA” presented by Don Stephens of the JTRS JPEO

Abstract: The original Software Communications Architecture (SCA) specification did not include special consideration for the unique capabilities of Field Programmable Gate Arrays (FPGAs) or Digital Signal Processors (DSPs). Generalized Application Program Interfaces (APIs) for the DSPs and FPGA were released as part of the Joint Tactical Radio System (JTRS) Infrastructure, but the Modem Hardware Abstraction Layer (MHAL) API was based upon a 'push' model that mimics CORBA interfaces. It is highly abstracted and readily implemented with serial communication paths between processing elements.

While very extensible and scalable, the MHAL does not exploit the full capabilities of today's FPGAs and DSPs. Abstraction has been achieved at a cost of increased hardware/CPU resources, latency, and data copying. Although it supports serial interfaces between processors, it limits the exploitation of parallel address buses, interrupts, and many other hardware features such as shared memory. An MHAL revision is in process that retains the scalability and extensibility of the original interface, but offers size, weight and power (SWAP) improvements in addition to improved communication response and performance.

About the Speaker: Donald R. Stephens, PhD, JPEO JTRS - San Diego.
Dr. Stephens is the Standards Manager. His team is responsible for the establishment and standardization of the JTRS infrastructure. They are responsible for the various standards defined by the JTRS program including the SCA, APIs, and other interfaces and standards. He has lengthy development experience with software radios; including the Digital Modular Radio (DMR), the Joint Tactical Terminal (JTT), and the Airborne Integrated Terminal Group (AITG). Don has professional experience with Raytheon E-Systems, McDonnell Douglas, Emerson Electric, and Scientific Atlanta. He has participated in all technology facets of software radio design such as RF, DSP, distributed computing, security, and networking.

3:30 to 4:00 “OCP Corporate Introduction” presented by Ian Mackintosh, President and Chairman of Open Core Protocol International Partnership (OCP-IP)

Abstract: This presentation will provide an overview of the Open Cores Protocol, and will show how OCP supports design reuse in FPGA based applications.

About the Speaker: Ian Macintosh is the Chairman and President of OCP-IP. Mr. Mackintosh is well known in the EDA and Semiconductor industries as an ASIC pioneer with a background in semiconductor design, software development and business management. Mr. Mackintosh, founder of OCP-IP, has been historically on the Boards of groups dedicated to SoC development and IP exchange through open standards and has also chaired working group activity developing Standards for and investigation in, IP Protection. Since 1980, he has held various senior management positions with National Semiconductor, VLSI Technology (now NXP), PMC-Sierra, Mentor Graphics and several start-up companies. He holds a Masters of Science from Southampton University, England